DRAM memory devices are comprised of individual memory cells. The surface area of each of the individual memory cells necessarily decrease as the DRAM device becomes more integrated. Each memory cell of a DRAM device contains a charge-storage capacitor for storing the memory information. As the size of the memory cell decreases, the effective area of the charge-storage capacitor in each memory cell decreases, which results in a decreased capacitance of the charge-storage capacitor. This decrease of charge-storage capacitance inevitably results in an increase of soft errors caused by the increased inflow of noise charges generated by alpha particles. Therefore, the higher integration of DRAM devices has necessitated a decreased cell size without a decrease in the charge-storage capacitance. Therefore, the effective area of a capacitor must be expanded in a decreased memory cell.
In order to satisfy, this requirement, a stack capacitor (STC) memory cell structure has been under development since the late 1970's. The general structure of the STC memory cell is as follows. AMOS transistor is formed within an active region of a semiconductor substrate, and a capacitor is connected through a buried contact to a source region of the MOS transistor. The storage electrode of the capacitor is horizontally extended to the upper part of the transistor's gate electrode and centered on the buried contact, thereby forming a memory cell having a stacked capacitor structure. This structure can increase the effective area of a capacitor formed between the above storage electrode and a plate electrode formed to correspond to the storage electrode.
A conventional STC memory cell is manufactured as follows. First, a MOS transistor is formed in the active region of a semiconductor substrate. A high temperature oxide (HTO) film is then formed to insulate the gate electrode of the MOS transistor, and a buried contact is formed over the source region of the MOS transistor. Thereafter, polysilicon is deposited for forming a storage electrode, which is then patterned by a conventional photolithography process, thus forming the storage electrode of the capacitor. After that, a dielectric film and plate electrode are formed to correspond to the above storage electrode, and a bit line is formed to complete the STC memory cell.
However, the conventional manufacturing method of the STC memory cell has the disadvantage of a reduced absolute effective area of the storage electrode in accordance with the decreasing cell size due to the higher integration of semiconductor memory devices. Therefore, the above STC memory cell structure is not suitable in manufacturing a DRAM device whose integration is beyond a real limit, e.g., 16 Mb.
Another conventional method of manufacturing an increased capacitance in a memory cell uses a high dielectric film, i.e., tantalum oxide (Ta.sub.2 O.sub.5). However, when tantalum oxide is used, leakage current is increased as compared with the use of silicon oxide or silicon nitride.
Another conventional method of increasing the memory cell capacitance is the use of a trench capacitor, wherein a trench is formed in a semiconductor substrate and a capacitor is formed inside the trench. However, in highly integrated DRAM devices, e.g., 16 Mb devices, isolation of the capacitors of adjacent memory cells without interference is very difficult to achieve.
A fin-structured capacitor has been proposed to increase cell capacitance by means of expanding the effective area of a capacitor. The fin-structured capacitor is a type of stacked capacitor which includes a storage electrode consisting of multiple spaced conductive layers. The top, bottom and side surfaces of each conductive layer can be used as effective area of the capacitor, therefore this structure is very advantageous to high integration of DRAM devices.
A conventional method for manufacturing the above fin-structured capacitor is explained as follows with reference to FIGS. 1-5. See also the article entitled "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS" by T. Ema et al., IEDM '88, pp. 592-595.
FIG. 1 is a sectional view showing a transistor formed in the active region of a semiconductor substrate, whereon alternating layers of insulating and conductive materials are deposited.
A conventional LOCOS isolation method is performed on a semiconductor substrate 1 such that a non-active region composed of a field oxide film 2 can be distinguished from an active region. AMOS transistor is formed on the field oxide film 2 comprising a gate insulating film 3, a gate electrode 4, a source region 5 and a drain region 6 formed in the active region. A wordline 4-1 is formed on the field oxide film 2 by patterning simultaneously when the gate electrode 4 is patterned.
A nitride film 7 is then formed on the whole surface of the resultant structure as an etching blocking layer to insulate the gate electrode 4. Then, a first insulating layer 8a of, i.e., silicon oxide, a first conductive layer 9a of, i.e., polysilicon, and a second insulating layer 8b of, i.e., silicon oxide, are successively formed on the nitride film 7.
A fin structure is then formed. For example, a two-tiered silicon oxide layer and a single polysilicon layer are alternately formed into a two-fin structure. Likewise, three layers of silicon oxide and two layers of polysilicon therebetween form a three-fin structure.
A contact hole is formed on the source region 5 by applying a mask pattern. The contact hole connects the source region 5 and a storage electrode of the capacitor.
Thereafter, a second conductive layer 9b of, i.e., polysilicon is formed by depositing polysilicon on the whole surface of the semiconductor substrate including the contact hole, whereon the first and second silicon oxide layers 8a, 8b and a first polysilicon layer 9a have been sequentially formed.
FIG.3 is a sectional view showing the formation of the storage electrode pattern of the capacitor. An etching step is performed by applying a mask pattern which leaves selective portions of the first and second polysilicon layers 9a, 9b and the second oxide layer 8b within a predetermined range centering on the contact hole.
FIG. 4 is a sectional view showing a completed storage electrode of the conventional capacitor. The second oxide layer 8b (which remains between the first and second polysilicon layers 9a, 9b) and the first oxide layer 8a are removed by wet-etching, thereby completing the fin-structured storage electrode 9. The nitride film 7 works as an anti-etching layer to prevent the underlying transistor from being damaged by the etching process.
FIG. 5 is a sectional view showing a completed capacitor and a bit line. A dielectric film 13 is formed on the upper surface of the storage electrode 9. A polysilicon layer is then deposited on the whole resultant surface, and patterned to form a plate electrode 14. Thereafter, an insulating film 15 is formed to insulate the plate electrode 14 from the bit line 16. The bit line 16 is formed by depositing a conductive material on the whole resultant surface after a contact hole is formed over the drain region 6.
The conventional fin-structured capacitor as disclosed by T. Ema can improve the effective surface area of the capacitor assuring sufficient memory cell capacitance, but problems still exist with the conventional method of manufacture.
First, reactive ion etching is used as the etching process for forming the storage electrode pattern by alternately etching polysilicon and silicon oxide layers. This method is overly complicated and damages the surface of the storage electrode due to changes in the etching process conditions for each layer, resulting in a deterioration of the reliability of the memory cell capacitance.
Second, a stringer is apt to be generated in the peripheral circuit region of the memory cell when the silicon oxide layer and polysilicon layer are sequentially etched if the over-etch process for their removal is insufficient.
Third, since the conventional fin-structure forms a storage electrode which is vertically multi-layered, the resulting cell topography becomes very poor. In addition, a photolithography margin for forming the contact hole and the storage electrode pattern in the conventional fin-structured device is reduced.